1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having transistors of CMOS structure, and a method of manufacturing the same semiconductor integrated circuit device.
2. Description of the Background Art
With the remarkable advance of semiconductor circuit devices (i.e., ICs and LSIs) to higher density and higher integration, recently, the semiconductor elements have been miniaturized more and more. For higher integration, although MOS FETs (Metal-Oxide-Semiconductor Field Effect Transistors) are advantageous, the power consumption within the chip also increases with increasing integration of the semiconductor integrated circuit device. Accordingly, CMOS devices having CMOS (Complementary MOS) structure FETs is suitable when a higher integration and a lower power consumption are both required.
To further miniaturize the semiconductor elements, a MOS FET of the structure as shown in FIG. 9 is conventionally proposed (as disclosed in Japanese Patent Laid-open No. 21730/1993 relating to Japanese Patent Application No. 198282/1991). This semiconductor element is preferably applied to a CMOS semiconductor integrated circuit, for instance. This element is formed on an N-type silicon semiconductor substrate 1 whose impurity concentration is about 2.times.10.sup.15 cm.sup.-3. The MOS FET is arranged in a double impurity diffusion region (referred to as a well, hereinafter) formed on the semiconductor substrate 1. Although not shown, other elements are formed directly in the semiconductor substrate or in other wells or other double wells.
The method of manufacturing the above-mentioned conventional semiconductor device (MOS FET) will be described hereinbelow: first boron ions are injected into the semiconductor substrate 1 with the use of a mask (not shown). The substrate is then heat-treated for several hours at about 1190.degree. C. to form a deep P well 6 with a depth (from the substrate surface) of about 5 .mu.m and a peak impurity concentration of about 6.times.10.sup.16 cm.sup.-3. Thereafter, phosphorous ions are further injected into the substrate 1. The substrate is then heat-treated for several hours to form a shallow N well 2 with a junction depth Xj (which is defined as a depth from the substrate surface) of about 1.0 .mu.m and a peak impurity concentration of about 6.times.10.sup.17 cm.sup.-3. Furthermore, element isolation regions (not shown) are formed on the surface of the semiconductor substrate 1 at interfaces between the semiconductor substrate 1 and the N well 2 and between the substrate 1 and the P well 6 in accordance with a selective oxidation technique such as LOCOS (localized Oxidation of Silicon). Then, a gate oxide film (SiO.sub.2) 4 with a thickness of 40 to 50 nm is deposited on the central surface portion of the N well 2. Next, boron ions are injected into the semiconductor substrate 1 through the oxide film 4 to control the threshold voltage (V.sub.th) of the MOS FET. Furthermore, a polycrystalline silicon (polysilicon hereinafter) film, for instance is deposited on the gate oxide film 4; phosphorus ions are diffused into the polysilicon film and further patterned to obtain a gate electrode 5. Further, boron ions are injected into the semiconductor substrate 1 from both sides of the gate electrode 5 and then thermally diffused to form a p.sup.+ source/drain region 3 whose impurity concentration of about 1.times.10.sup.21 cm.sup.-3.
In the MOS FET formed as described above, an internal supply voltage (V.sub.int) of 4 V is applied to the N well 2; a constant voltage V.sub.bb (-2 V) is applied to the P well 6; and a gate voltage V.sub.g is applied to the gate electrode 5. Further, a reverse bias voltage is applied to the two wells from the outside using the external contact V.sub.ext to control the operation of the MOS FET. This is because the capacity at a PN junction formed between the two wells can be controlled by a reverse bias voltage applied to the PN junction between the two wells.
In the conventional semiconductor integrated circuit, device of CMOS structure, the depth of the wells (both N and P wells) is 2 .mu.m or more from the surface of the semiconductor substrate; that is, the depth is about 4 to 5 .mu.m. In contrast, in the case of the structure formed with the shallow well 2 as shown in FIG. 9, the drain current increases as compared with other conventional circuit devices, and further the depletion layer capacitance under the channel region is coupled to the reverse bias capacitance between the N well 2 and the P well 6, with the result that the depletion layer becomes thicker than that obtained by a gate voltage applied and thereby the MOSFET can be activated substantially at a lower voltage.
However, in the conventional MOS FET of the structure, as shown in FIG. 9, in which the two wells are simply made shallow to miniaturize the semiconductor integrated circuit device, it is necessary to provide external electrodes for applying a voltage from the outside to the well region at which the MOS FET is formed, to the semiconductor substrate which forms a junction to this well region or to another well region which encloses this well region. In the case of the double well structure as shown in FIG. 9, on the other hand, since the well regions must be formed as shallow as possible for miniaturization, the outside well 8 must be formed as close as possible to the inside well 2 and therefore the outside well 6 cannot be substantially exposed on the surface of the semiconductor substrate 1, with the result that there arises a problem in that an open area at which the external electrode can be formed will not be obtained on the outside well 6.